IBM has revealed a new chip design called NanoStack that claims it can cram 100 billion transistors onto a surface the size of a fingernail. If the technology works as advertised, it would represent the world’s first known chip that operates below 1 nm.
Current mainstream chips sit around 2 nm in size. By shrinking the transistors to roughly 0.7 nm, IBM says the new design pushes the envelope further. The move to sub‑nanometre nodes should help manufacturers pack more logic into the same silicon area without increasing the power budget.
IBM’s internal tests show the NanoStack prototype is about 50 % faster and 70 % more energy efficient than its own 2 nm line. In prior work, IBM has quoted similar performance gains when it launched its 2 nm chips in 2021.
The core of NanoStack is a three‑dimensional stack: transistors are built as tall pillars and then layered on top of each other. This approach keeps the horizontal footprint constant while increasing vertical density, but it also creates heat problems and makes leakage a serious concern. Industry observers say competitors such as Samsung and Intel have begun 3‑D products that are roughly a third of the stack height, making IBM’s design the most ambitious to date.
While promising, the technology is still a few years away from commercial production. If realised, it could transform anything from smartphones to AI‑powered data centres, offering more power while keeping devices small and wallets light.
